1. Technical Field
The present invention relates to a manufacturing method for an active matrix substrate included in a television receiver, a personal computer and so forth, to the active matrix substrate and to a display apparatus including the active matrix substrate.
2. Description of Related Art
Among display apparatuses, a liquid crystal display apparatus has characteristics of being thin and consuming a small amount of electricity. Specifically, a liquid crystal display apparatus comprising an active matrix substrate having a switching element such as a thin film transistor (TFT) or the like for each pixel presents high performance including high contrast ratio and good response characteristics, and is thus preferably used for a television receiver, a personal computer, etc.
Multiple gate wirings (scanning wirings) and multiple source wirings (signal wirings), each of which crosses each of the gate wirings through an interlayer dielectric film, are formed on the active matrix substrate. The thin film transistor for switching a pixel is provided near the crossing part of the gate wiring and the source wiring.
Capacitance formed at the crossing part of the gate wiring and the source wiring (parasitic capacitance) is desired to be small, because it causes the deterioration of the display quality.
Japanese Patent No. 4450834 discloses the invention of an active matrix substrate in which the parasitic capacitance is reduced by an insulation film covering the gate wirings being configured as a multi-layered insulation film with a first insulator layer and a second insulator, in which the first insulator layer is constituted by an insulating material containing an organic constituent.
FIG. 20 is a schematic cross-sectional view illustrating a portion of a TFT structure of a prior art active matrix substrate according to Japanese Patent No. 4450834, etc.
As illustrated in FIG. 20, a gate electrode 11a (a part of a gate wiring 11) is formed on the glass substrate 10 of an active matrix substrate.
An interlayer dielectric film 14 constituted by SOG is formed to cover the substrate 10 and the peripheral part of the gate electrode 11a. At the inner side of the peripheral part of the gate electrode 11a, the interlayer dielectric film 14 has a contact hole 14a not covered by the interlayer dielectric film 14.
At forming the interlayer dielectric film 14 constituted by SOG, at first an SOG material is applied to form a coating film on the substrate 10 and the gate wiring 11 and then baked. Thereafter, a photoresist is formed on the coating film. The photoresist is exposed to light through a photomask and then developed to form a resist pattern. Next, the part of the coating film not covered by the resist undergoes etching, such as dry etching using mixed gas of tetrafluoromethane and oxygen, to form the contact holes 14a and so forth. Finally, the resist is removed.
A gate insulation film 15 is formed on the interlayer dielectric film 14 and the gate electrode 11a, and a first semiconductor film 16 is formed on the gate insulation film 15. In addition, a second semiconductor film 17 constituted by an n+ film is formed to cover the first semiconductor film 16.
A resist pattern 18 is formed to pattern the first semiconductor film 16 and the second semiconductor film 17.
Additionally, a film made of Cu or the like is deposited using, for example, a sputtering method on the second semiconductor film 17 which is obtained by being patterned with the resist pattern 18, or on the gate insulation film 15 which is exposed by the removal of the first semiconductor film 16 and the second semiconductor film 17. The deposited film is patterned to form source metal (not depicted) including source electrodes and the source wirings.
In the TFT structure described above, the interlayer dielectric film 14 is provided between the gate wirings 11 and the source wirings, which allows for manufacturing of a high definition display panel without increase in resistance of the wirings and deterioration of TFT driving.
At patterning using a lithography device, the film which is formed over the gate wiring 11 is aligned with the edge of the pattern of the wiring 11 to correct the overlaying position.
The resist pattern 18 is corrected so as to correct the positions of patterns of the first semiconductor film 16 and the second semiconductor film 17 both of which will be formed subsequently. At this time, the distance from the edge of the gate wiring 11 to the resist pattern 18 is measured with a microscope. Based on the measured result, the photoresist is formed again and then the resist pattern 18 is formed again using a photomask. The part not covered by the resist pattern 18 is etched thereafter to obtain the patterned first semiconductor film 16 and second semiconductor film 17.
FIG. 21A is a schematic view illustrating the relationship between the positions of the resist pattern 18 and the gate wiring 11 in the case where the interlayer dielectric film 14 is not present. FIG. 21B is a schematic view illustrating the resist pattern 18 in the case where the interlayer dielectric film 14 is present.
As illustrated in FIG. 21A, if the interlayer dielectric film 14 constituted by SOG is not present, the edge of the gate wiring 11 is visible, which facilitates the position adjustment of the resist pattern 18.
If the interlayer dielectric film 14 constituted by SOG is provided, as illustrated in FIG. 21B, a colored film such as the first semiconductor film 16 or the second semiconductor film 17 formed over the gate wiring 11 prevents the edge of the gate wiring 11 from being viewed. As illustrated in FIG. 20, the interlayer dielectric film 14 is formed so as to cover the edge (tapered part) of the gate electrode 11a. Because a large portion of incident light may be reflected on the reflection films inside the triple-layered film composed of the gate insulation film 15, the first semiconductor film 16 and the second semiconductor film 17, and because there is the interlayer dielectric film 14 between the back side of the gate insulator 15 and the gate wiring 11, the edge of the gate wiring 11 may hardly be viewed.
Therefore, the resist pattern 18 has its position adjusted by the pattern of the interlayer dielectric film 14 (the contact hole 14a in FIG. 21B). The resist pattern 18 is thereby incorrectly placed with respect to the edge of the gate wiring 11, which deteriorates the precision of overlaying. Specifically, while high overlaying precision is required for adapting the display panel to a high definition digital video format, such as Super Hi-Vision (8K Ultra High Definition Television, for example), the prior art poses a problem in that such a requirement is difficult to be met with.
In addition, because each lithography apparatus is generally given its condition setting depending on the film as a reference processed by each apparatus, the change of the condition setting of the apparatus that processes the resist pattern on the interlayer dielectric film 14 requires the condition resetting of the apparatus that processes the resist pattern on the upper film, causing a problem in that the forming process is complicated accordingly.
A hole for position adjustment may possibly be formed at the interlayer dielectric film 14 while going across above the edge of the gate wiring 11. However, because the forming process of the interlayer dielectric film 14 includes the dry etching process, as described above, the substrate 10 may be etched when the interlayer dielectric film 14 is not provided at the tapered part of the gate electrode 11a. In addition, a defect can be caused by abnormal electric discharge at the tapered part of the gate electrode 11a, which decreases the yield.
Therefore, the prior art includes a problem in that the hole for alignment cannot be formed on the interlayer dielectric film 14 except for the part on the gate wiring 11.
The present invention is made in consideration of the above-described circumstances. An object of the present invention is to provide a manufacturing method of an active matrix substrate, the method being capable of creating without etching of a substrate surface and abnormal electric discharge, in an interlayer dielectric film, a hole for alignment and being capable of easily correcting the position of a formed film with respect to the position of the film of the lowest layer, with high overlaying precision. Also, an object of the present invention is to provide the active matrix substrate and a display apparatus comprising the active matrix substrate.
A method of manufacturing an active matrix substrate according to one embodiment of the present invention comprises: forming, on a substrate, a gate wiring and a source wiring which crosses the gate wiring at an upper layer than the gate wiring; forming a thin film transistor near a region where the gate wiring and the source wiring face each other; and forming an interlayer dielectric film containing a spin-on-glass (SOG) material in at least an area between the gate wiring and the source wiring in the region, wherein the interlayer dielectric film is formed using the SOG material with photosensitivity, and a hole for adjustment of a pattern of a film which is formed at an upper layer than the substrate and the interlayer dielectric film is formed.
In the embodiment, because the interlayer dielectric film is formed using an SOG material with photosensitivity, a dry etching process is not required for forming the film, which prevents the problems of etching of the substrate surface and abnormal electric discharge, and this allows an aperture for alignment to be formed at a portion other than a film on the lower side of the interlayer dielectric film, for example in the interlayer dielectric film itself. Accordingly the adjustment of overlaying can be conducted based on the pattern of the film of the lower layer, this improves the overlaying precision.
Therefore, according to the embodiment, as the active matrix substrate can be manufactured in the situation that the position adjustment is facilitated, defects are reduced and the yield is improved.
The method according to the embodiment of the present invention may comprise a step of forming the gate wiring on the substrate before forming the interlayer dielectric film, wherein the hole is formed to make an edge of the gate wiring visible.
In the embodiment, because overlaying is adjusted based on the edge of the gate wiring which is a layer provided right over the substrate, namely the lowest layer, the overlaying precision is further improved.
In the method according to the embodiment of the present invention, it is preferred that the hole is formed to go across above the edge of the gate wiring.
In the embodiment, the edge of the gate wiring is certainly visible.
The method according to the embodiment of the present invention may comprise a step of forming a semiconductor film at an upper layer than the gate wiring while viewing the edge of the gate wiring through the hole.
In the embodiment, the interlayer dielectric film and the semiconductor film can be patterned based on the pattern of the gate wiring, which improves the overlaying precision.
The method according to the embodiment of the present invention may comprise a step of forming a source metal which includes the source wiring or a source electrode at an upper layer than the semiconductor film while viewing the edge of the gate wiring through the hole
In the embodiment, the interlayer dielectric film, the semiconductor film and the source metal can be patterned based on the pattern of the gate wiring, which improves the overlaying precision.
A method of manufacturing an active matrix substrate according to one embodiment of the present invention comprises: forming, on a substrate, a gate wiring and a source wiring which crosses the gate wiring at an upper layer than the gate wiring; and forming a thin film transistor near a region where the gate wiring and the source wiring face each other; further comprises: forming the gate wiring on the substrate; forming an interlayer dielectric film using an SOG material with photosensitivity on a surface of the region of the gate wiring crossing the source wiring; and depositing a film on the interlayer dielectric film, the substrate and the gate wiring while viewing an edge of the gate wiring.
In the embodiment, because the interlayer dielectric film is formed only at the crossing part of the gate wiring and the source wiring, the patterning can favorably be adjusted while viewing the edge of the gate wiring, when a film is deposited on the interlayer dielectric film as well as on the upper side of the substrate and the gate wiring not provided with the interlayer dielectric film.
In the method according to the embodiment of the present invention, it is preferred that the SOG material contains a diazonaphthoquinone derivative, a solvent, and at least two kinds of polysiloxanes with different rates of solubility to tetramethylammonium hydroxide water solution.
In the embodiment, the SOG material has good photosensitivity and the interlayer dielectric film has good thermal resistance, transparency and insulation property.
An active matrix substrate according to one embodiment of the present invention comprises: a gate wiring and a source wiring which crosses the gate wiring on the upper side of the gate wiring, formed on a substrate; a thin film transistor formed near a region where the gate wiring and the source wiring face each other; and an interlayer dielectric film containing a spin-on-glass (SOG) material and being interposed in at least an area between at least the gate wiring and the source wiring in the region, wherein the interlayer dielectric film is formed using the SOG material with photosensitivity and has a hole for adjustment of a pattern of a film formed at an upper layer than the substrate and the interlayer dielectric film.
In the embodiment, because the interlayer dielectric film is formed using the SOG material with photosensitivity, because dry etching is not required for forming the film, and because the problems of etching of the substrate surface and abnormal electric discharge are prevented, the hole for alignment is provided at a portion other than a film on the lower side of the interlayer dielectric film, for example in the interlayer dielectric film itself. Therefore, the upper film is precisely overlaid based on the pattern of the film of the lower layer.
A display apparatus according to one embodiment of the present invention comprises: the above-mentioned active matrix substrate, and an opposite substrate opposed to the active matrix substrate through the display medium layer.
In the embodiment, the display apparatus can be designed for higher definition because the display apparatus comprises the active matrix substrate described above.
According to the embodiment of the present invention, because the interlayer dielectric film is formed using the SOG material with photosensitivity, the hole for alignment can be provided in the interlayer dielectric film, namely at a portion other than a film on the lower side of the interlayer dielectric film, without etching of the substrate surface and abnormal electric discharge. The hole may be used for correcting the position of the film formed over the interlayer dielectric film to be aligned with the position of the lowest layer, and thus the film may be deposited with high overlaying precision.
Therefore, according to the embodiment of the present invention, the active matrix substrate can be manufactured while the position adjustment is facilitated, the occurrence of defects is suppressed and the yield is improved, so that the display apparatus may be designed for high definition and be adapted for a larger size.
The above and further objects and features will more fully be apparent from the following detailed description with accompanying drawings.